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The Mira system is based on IBM's next-generation PowerPC SoC, in this case the 16-core Power A2 processor (PDF), a 64-bit CPU capable of handling 4 threads simultaneously. The processor has 32 KB of L1 cache -- 16 KB for data and 16 KB for instructions. L2 cache is made up of 8 MB of embedded DRAM (eDRAM ), a high-density on-chip memory technology that IBM uses for Blue Gene and its latest Power7 processors. Memory and I/O controllers are integrated on-chip.
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The Mira system is based on IBM's next-generation PowerPC SoC, in this case the 16-core Power A2 processor ([https://wiki.mcs.anl.gov/nekcem/index.php/File:Wire.pdf PDF]), a 64-bit CPU capable of handling 4 threads simultaneously. The processor has 32 KB of L1 cache -- 16 KB for data and 16 KB for instructions. L2 cache is made up of 8 MB of embedded DRAM (eDRAM ), a high-density on-chip memory technology that IBM uses for Blue Gene and its latest Power7 processors. Memory and I/O controllers are integrated on-chip.
  
 
Each server node will contain a single A2 processor and sport either 8 or 16 GB of memory. A fully populated Blue Gene/Q rack contains 1024 nodes, representing 16K cores. I/O has been split from the server nodes so that configurations can scale compute and I/O independently. A rack can accommodate between 8 and 128 I/O nodes. Conveniently, the I/O nodes use the same Power A2 chip as the compute servers.
 
Each server node will contain a single A2 processor and sport either 8 or 16 GB of memory. A fully populated Blue Gene/Q rack contains 1024 nodes, representing 16K cores. I/O has been split from the server nodes so that configurations can scale compute and I/O independently. A rack can accommodate between 8 and 128 I/O nodes. Conveniently, the I/O nodes use the same Power A2 chip as the compute servers.

Revision as of 15:42, 17 February 2011

The Mira system is based on IBM's next-generation PowerPC SoC, in this case the 16-core Power A2 processor (PDF), a 64-bit CPU capable of handling 4 threads simultaneously. The processor has 32 KB of L1 cache -- 16 KB for data and 16 KB for instructions. L2 cache is made up of 8 MB of embedded DRAM (eDRAM ), a high-density on-chip memory technology that IBM uses for Blue Gene and its latest Power7 processors. Memory and I/O controllers are integrated on-chip.

Each server node will contain a single A2 processor and sport either 8 or 16 GB of memory. A fully populated Blue Gene/Q rack contains 1024 nodes, representing 16K cores. I/O has been split from the server nodes so that configurations can scale compute and I/O independently. A rack can accommodate between 8 and 128 I/O nodes. Conveniently, the I/O nodes use the same Power A2 chip as the compute servers.

Server-to-server communication is performed over a 5D Torus, which is capable of up to 40 gigabits per second, four times the speed of the Blue Gene/P interconnect. The 5D Torus employs fiber optics, the first Blue Gene design to do so.

Compute performance is delivered by using a large number of relatively low-speed cores -- a hallmark of the Blue Gene architecture. Unlike the speedy 3.3 GHz Power7 chips that will go into the future Blue Waters supercomputer at the NCSA, the A2 processor for Blue Gene hums along at a modest 1.6 GHz (although faster versions of this chip can hit 3 GHz). According to IBM, Mira will encapsulate 750K cores, which works out to about 48,000 CPUs. Total memory is 750 TB, backed by 70 petabytes of disk storage.

The low-speed, high-core approach makes for a very energy-efficient package. A Blue Gene/Q prototype grabbed first place on the November 2010 Green500 list, with a Linpack rating of 1684.2 megaflops/watt. That bested even the latest Fermi GPU accelerated supers, like the TSUBAME 2.0 system recently installed at Tokyo Tech, as well as IBM's fastest Cell (PowerXCell 8i) processor-accelerated QS22 clusters. To further boost energy efficiency and maintain reliability, all Blue Gene/Q racks are water cooled.

Because of its size, Argonne is looking at Mira as a stepping stone to exaflop supercomputing. With less than a million cores though, programmers will have to use some imagination to scale their codes to the hundreds of millions of cores envisioned in a true exascale system.

However, by the time IBM and others start building such machines, the Blue Gene PowerPC-based architecture is likely to be subsumed into the company's Power-based line-up (which at the processor ISA level, at least, is quite similar). Based on a recent conversation with Herb Schultz, marketing manager for IBM's Deep Computing unit, the Power and Blue Gene lines may merge around the middle of this decade. That would suggest that Blue Gene/Q could very well be the last in the Blue Gene lineage.